Page Comparison

Physical Fuse Selection

In regulation 8.5.b, it states, “All other wiring branching off the main bus circuit must have properly sized fuses. Fuses must be located near the branch point, either within the same enclosure or before a reduction in rated conductor ampacity.” This means we can't rely solely on the eFuse, and we need to place a physical fuse in series to act as backup protection.

The physical fuse will be selected to a current specification above the maximum of the eFuse so that the eFuse, which requires minimal manual intervention to reset, should trip first and save the physical fuse.

As the fuse will only be required to act when there is a failure to do so by the eFuse, a very rare occurrence, we will be prioritizing size in our selection of physical fuse.

eFuse Parts Selection

eFuse IC: TPS25983 (

View file
name tps25983.pdf

)

This eFuse IC was selected because…

• Its wide 2 - 18 A current limit range allows flexibility without needing to parallelize any eFuses.

• Has functionality for overcurrent, under/overvoltage, slew rate control, reverse current (via external FET). (Note that we will be implementing undervoltage protection ourselves so that the EN/UVLO pin can be used as an EN pin for switching of outputs.)

• Monitoring functionality for current and fault state.

• Works for 12V and 24V systems.

It’s on the more pricy side of TI eFuses but the wide current range and flexibility in voltage will allow us to save costs by requiring fewer ICs if we can keep the same system working into the next-generation vehicle.

Note that we will want the circuit breaker variant of this eFuse and not the current limiting variant.

Calculated Component Values for eFuse Protection Functions

Overcurrent Limit Resistor

According to the datasheet, the formula for determining the resistance of a particular current limit is…

$ R_{ILIM} (\Omega) = \frac{1460}{I_{LIM} (A) - 0.11}$

For a current limit range of 2 - 18 A, a range of possible goes from 81.610 Ω to 772.487 Ω.

...

On the BBPDU, we will be using a digital POT IC to be able to easily change the current limit through code. Its selection is described in a section below.

Overcurrent Blanking Interval Capacitor

The overcurrent blanking interval is the period where a current past the limit threshold is ignored for a time period. This is used to help deal with transients and avoid false alarms.

The overcurrent blanking interval is defined as…

$t_{ITIMER} (ms) = \frac{C_{ITIMER} (nF) * \Delta V_{ITIMER} (V)}{I_{ITIMER} (\mu A)}$

Where the capacitance for a specific blanking interval is…

$C_{ITIMER} (nF) = \frac{t_{ITIMER} (ms) * I_{ITIMER} (\mu A)}{\Delta V_{ITIMER} (V)} = \frac{t_{ITIMER} (ms) * I_{ITIMER} (A)}{\Delta V_{ITIMER} (V) * 10^6}$

We can find I_ITIMER and ΔV_ITIMER in the Electrical Characteristics on p. 8 of the eFuse datasheet. With their typical values, we can simplify this to be…

$C_{ITIMER} (nF) = \frac{t_{ITIMER} (ms)}{0.467}$

Additionally, we can leave the pin open for no blanking interval. Do not short the ITIMER pin to ground.

Decision: We will leave the pin open for no blanking interval by default and determine proper blanking intervals on a case-by-case basis depending on the amount of inrush.

Current Monitoring Resistor

The current monitor works by creating a proportional current to the one flowing through the eFuse.

According to the datasheet, the formula for determining the a particular load current is…

$ I_{LOAD} (A) = \frac{V_{IMON}(\mu V)}{R_{IMON} (\Omega) * G_{IMON}(\mu A/A)}$

The G_IMON is a proportionality constant given in the electrical characteristics to be 243 uA/A.

Rearranging this to solve for the value of R_IMON that we wish to use… (as shown on p. 24 of the datasheet)

$ R_{IMON} (\Omega) = \frac{V_{IMON}(\mu V)}{I_{LOAD} (A) * G_{IMON}(\mu A/A)} = \frac{V_{IMON}(V)}{I_{LOAD} (A) * G_{IMON}(\mu A/A)*10^{-6}}$

• Our ADC can read a maximum value of 2.5V (based on voltage reference provided to the ADC), so V_IMON = 2.5 V.

  • Table 8-2 of the eFuse datasheet recommends using a lower V_IMON to “ensure the IMON pin internal amplifier has sufficient headroom to operate linearly.” For V_IN > 5V, it recommends a maximum V_IMON of 3.3V, which is met with our selection.

• The maximum ILOAD of the eFuse is 18 A. Although most, if not all, of our outputs will not utilize that full quantity, we will design for the full range of possible values to avoid having to resolder IMON resistors in the future. This will reduce our precision when reading the current as a tradeoff.

$R_{IMON}(\Omega) = \frac{2.5*10^6}{18 * 243} = 571.559 \Omega \rightarrow 549 \Omega $

To measure the full range of currents, we need a 571.559 Ω resistor. Finding a close-by standard resistor size, we moved down to 549 Ω ensure that in the event of an overcurrent event greater than 18A, we’d still be able to measure it to a degree without exceeding the ADC’s limits (or even worse, damaging the ADC IC). With 549 Ω, the largest current we can measure is 18.740 A nominal (with 1% resistor, 18.554 - 18.929 A).

Read the voltage drop across the resistor to find the current through the eFuse. Add a low-pass filter to smooth the results and prevent aliasing in the ADC conversion.

Result: Install a 549 Ω 1% resistor from IMON to ground.

Retry Delay

The delay before retry attempts after a fault is determined by…

$t_{RETRY\_DLY} (\mu s) = \frac{128 * (C_{RETRY\_DLY} (pF) + 4 pF) * V_{RETRY\_DLY\_HYS} (V)}{I_{RETRY\_DLY} (\mu A)}$

Solving for the capacitance at the RETRY_DLY pin…

$C_{RETRY\_DLY} (pF) = \frac{t_{RETRY\_DLY} (\mu s)*I_{RETRY\_DLY} (\mu A)}{128*V_{RETRY\_DLY\_HYS} (V)} - 4pF$

(or just use the table at the end of the Retry # of Attempts section for some common values.)

Note: the Retry # of Attempts capacitance depends on this value. If a change is made here, NRETRY needs to be reevaluated.

Result: We will implement a 915 ms delay, resulting in a 22 nF capacitor to ground at the RETRY_DLY pin.

Retry # of Attempts

The capacitance value for number of retry attempts depends on what capacitance you picked for retry delay.

$N_{RETRY} = \frac{4 * I_{RETRY\_DLY}(\mu A) * C_{NRETRY}(pF)}{I_{NRETRY}(\mu A) * (C_{RETRY\_DLY}(pF) + 4pF)}$

Solving for the amount of capacitance for a certain N retries…

$C_{NRETRY}(pF)= \frac{N_{RETRY}*I_{NRETRY}(\mu A) * (C_{RETRY\_DLY}(pF) + 4pF)}{4*I_{RETRY\_DLY}(\mu A)}$ 

Note that N can only consist of the set of values {(0), 4, 16, 64, 256, 1024, inf}. Any value not equal to these will be rounded up.

For an infinite amount of attempts, short NRETRY to ground. For no auto-retry (latch off), short RETRY_DLY to ground (NRETRY does not matter).

For a set of common RETRY_DLY and NRETRY values…

...

Result: We will implement 4 retry attempts. With the previously selected 915 ms delay between each, we will place no capacitor between NRETRY and ground (open).

Slew Rate

The integrated output slew rate helps control large inrush current. The formula for determining the slew rate of a particular load capacitance is…

$ SR(V/ms) = \frac{I_{INRUSH}(mA)}{C_{OUT}(\mu F)}$

According to the datasheet, the formula for determining the capacitance of a particular slew rate is…

$ C_{dVdt} (pF) = \frac{4600}{SR(V/ms)}$

It is recommended to select a capacitor with a value 20% higher than the calculated one and then choose the closest available capacitor from the 10% tolerance series. This is because the dV/dt capacitor experiences approximately VIN + 4 V during startup, and the high voltage bias causes a reduction in the effective capacitance.

Overvoltage Lockout

According to the datasheet, the formula for determining the OVLO for a given power supply is…

$ V_{IN}(OV) = \frac{V_{OV}*(R1+R2)}{R2}$

The eFuse turns OFF the power to the output when the voltage at the OVLO pin is greater than the OVLO rising threshold, VOV(R). The output power is turned ON again after the voltage at the OVLO pin falls below the OVLO falling threshold, VOV(F).

To have a overvoltage lockout threshold at VIN = 12.8V:

$ 12.8 = \frac{1.21*(R1+R2)}{R2}$

To achieve this, we can use R1 = 976k and R2 = 102k.

Gate Resistance (for external FET)

Picked from reference design.

External FET: CSD17573Q5B (

View file
name csd17573q5b.pdf

)

The TP25983 offers the ability to drive the gate of an external FET to block reverse current.

This MOSFET was picked because it is what’s used in TI’s development board for the eFuse we’re using. It wasn’t clear what requirements there were for external FETs on the eFuse datasheet so we’re using a MOSFET that is known to work. This also means we don’t have to decide the gate resistance ourselves.

• We need to ensure whatever voltage the BGATE pin is at is sufficient for the MOSFET of choice so that the MOSFET stays in the linear region. However, the voltage BGATE works at is not clear. Page 35 of the eFuse datasheet states that “The dVdt capacitor is subjected to typically VIN + 4 V during startup”, but unsure about regular operation.

Digital POT IC: AD5258BRMZ1 (

View file
name AD5258.pdf

)

The current limit is set on the eFuse IC using a resistance from the ILIM pin to ground. In order to allow this limit to be easily adjustable without replacing components or opening up the PCB’s enclosure, we will use a digital potentiometer/rheostat IC.

This digital POT IC features a range from about 150 Ω - 1150 Ω, which covers the range of resistances calculated above that we need to be able to set the eFuse. It doesn’t fully cover the lower end of resistance values, but that is for very high current limits that we are unlikely to set.

Another potential option could be the AD8400. It has a smaller package, more resistance positions, and a smaller package, but is significantly more expensive.

I2C Mux: PCA9544A

• First one that showed up when Googled for I2C mux. Seems to fit purpose.

Monitoring Parts Selection

SOM:

fwef

Analog MUX: ADS7953SBDBT (

View file
name ads7953.pdf

)

• Same as what BPS is using.

Reference Voltage: MIC5317-2.5

• Same as what BPS is using.

SPI I/O Expander: MCP23S17 (

View file
name MCP23017-Data-Sheet-DS20001952.pdf

)

(I2C equivalent: MCP23017)

• Offers both SPI and I2C variant.

• Has interrupt pin(s).

• Has addressing system in SPI which provides more flexibility.