2022 - 2024 Power Systems Retrospective

Timeline

• Pre-competition (summer):

  • Power Board:

    • Many issues

    • Fried two Nucleos when testing.

    • Spent several days debugging a strange error causing an oscillation in our power output. We had initially thought it was caused by a shorting between the main and supplemental power sources, but it turned out to be some innate wire resistance causing the software to switch when it didn’t have to. The error was resolved by some software threshold tuning.

    • The overall architecture for the Power board was incredibly flawed:

      • We were “bootlegging” the Nucleo’s power. In other words, the Nucleo turned on and off the power it itself relied on. We (mistakingly) settled for less and relied on some leakage current to boot up the Nucleo which wasn’t consistent at all.

      • The power board’s handling of LV enable missed some critical aspects of our current electrical architecture. To summarize, LV Enable was previously connected to a NMOS gate that branched our Power board output to GND. The critical detail we missed was the fact that there was a path to GND through controls (Power board → Fuse box → controls or possibly Power board → Fuse box → contactor driver → controls). This caused LV to receive power despite LV Enable being off.

      • Fix: both issues were fixed by a quick Power board architecture redesign done by Tianda. We connected the Nucleo to the supplemental batteries so that its power wouldn’t be bootlegged anymore. To solve the LV Enable issue, we removed the NMOS, connected the output to GND, and instead opted to use software signal to control LV Enable instead. We recieved the 12V LV Enable signal from controls, fed it to a 12V → 3.3V LDO and read that signal using another GPIO on the nucleo. From there, it was a simple software AND logic using LV Enable.

    • Never had the time to perfectly tune the Power board threshold values but we didn’t experience any issues with it.

  • Contactor Driver board:

    • Used only one to drive both Motor and Array pre-charge contactors.

    • Moved the pre-charge resistors off the boards and next to the contactors.

  • Battery:

    • Several spotwelds failed and had to be replaced. The braided wire for the Battery output connection also broke.

  • HV:

    • Wiring went relatively smoothly but it was still clear that boards were not designed with integration in mind.

• Competition

  • Power Board:

    • Had a GND loop issue. This is through the same paths as listed before in the LV Enable issue. This caused some strange behavior where the non-critical fusebox would somehow receive power even when the main battery wasn’t active (which was the only requirement for the non-critical fusebox to receive power). The solution was to eliminate the GND loop by disconnecting the GND wires for controls power contactor driver signals.

    • There was also no protection on the power line that was getting read by the ADC. Therefore, it was very susceptible to getting incorrect readings or maybe even getting damaged by transients on the power line. We should have had at least a TVS diode on the line for protection.

  • No issues with the battery or HV

General Notes for the next cycle

• Let more mechanical limitations be placed on electrical systems.

  • Easier for electrical systems to make changes last-minute compared to mechanical systems.

  • Allows for easier integration. Wiring for Daybreak was a nightmare because each electrical systems didn’t consider the feasibility of wiring during the design of boards. Allowing mechanical systems (especially EMech) to set guidelines early on will make future integration a lot less of a hassle.

• Implement a more rigorous testing and design procedure.

  • Use simulation software such as LTSpice to model our more hardware based circuits before working on a PCB.

  • Have cross-system reviews to gain a more diverse opinion on decisions made.

  • Add more hardware debugging (reference the BPS Leader board which has numerous LEDs indicating different faults and testpoints).

  • We will have a more specific and holistic QUAC for board designs for the next cycle.

  • Be more iterative when testing - break down every project into a series of smaller tests.

  • Back up decisions with research.

• Prioritize testing current-gen goals earlier.

  • Prime example of delayed testing that caused an unfortunate amount of errors is the Power Board.

  • We will be better utilizing ClickUp - see it as a resource and not a chore.

  • We need to be setting harder deadlines on when certain things need to be validated - stricter scheduling goes in tandem with our plans for a more iterative testing procedure.